DAC 2018 - Tagged with Topic Area>Design

Designer and IP Track Poster

124.17 - Functional Equivalence Verification, Not Just RTL to Netlist

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.18 - Low Power Design by Placement Optimization in 7nm

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.19 - Layout Constrain Checks for Analog and Automotive Design

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.1 - Implementing Design-for-Test within a Tile-based Design Methodology using Tessent® Shell and IEEE 1687

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.20 - A Novice’s Experience with Formal Connectivity Check: Visibility, Capacity, Performance, Debug and Closure

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.21 - Pre-CTS Power Integrity and Timing Optimization in Advanced Process Nodes

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.22 - Load-Aware Memory DVFS in Mobile SoC

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.23 - Well Dependent Gate Antenna Rules

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.24 - A New IP Layout Review and Evaluation Flow

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.25 - Bridging the Gap Between RTL & Gate Level Power Estimation in DSP Core of Advance Process Node Smartphone Chip

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.27 - Challenges and Approaches of PI Signoff for Next Generation Large Scale Network Chips

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.28 - Rapidly Building Next Generation Web-based EDA Applications and Platforms from Legacy Tools

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.29 - Reusing Test Firmware from IP to SoC

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.2 - A Smart Layout Merging and Review Flow for Multi_core Server CPU Design

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.3 - Novel Method for Prognosis of Plausible IR Violation Prone Regions in SOC

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.4 - A High Efficiency SPICE Accuracy Timing Closure Flow

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.5 - Architectural Formal Verification of a Coherency Manager

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.6 - Methodology to Improve Analog Sub-system Layout Utilization

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.8 - Network-on-Chip Floorplanning Automation

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.9 - A Comprehensive Approach to Clock and Reset Domain Crossing Analysis Sign-off

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session