DAC 2018 - Tagged with Topic Area>Design

Designer and IP Track Poster

123.25 - Multi-cycle Path Exceptions Automation and Verification Methodology

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.26 - Integrated ESD Solution: How Various ESD Checks can be Integrated in a Single Flow for Efficient Analysis

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.2 - Soft-IPs Protection using Chaotic Map-based Encryption

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.2 - Technical Director, Automotive Applications Engineering

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.3 - High Quality Test with Efficient usage of Optimal Number of I/Os

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.4 - Novel and Configurable Circuit for Post-Silicon Measurement of Dynamic and Leakage Power of Sequential Circuits

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.5 - Solving the Flash Incompatibility Issue

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.6 - System in Package Power Integrity Analysis of Large Scale FPGA

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.7 - More than UVM/RTL Simulations: Compelling need for Hybrid Verification-Validation for SOC Class FPGA Designs

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.8 - Identifying and Fixing Power Leaks

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.8 - Methodology for SoC-level PDN Analysis to Measure Inrush & Droop during Ramp-up/Ramp-down Cycle

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

123.9 - Advantages and Pitfalls for Hierarchical CDC Analysis

5:00 PM–6:00 PM Jun 25, 2018 (America - Los Angeles)

Designer IP Poster Session

Research Reviewed

12.3 - Multi-Objective Bayesian Optimization for Analog/RF Circuit Synthesis

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 3018

Designer and IP Track Poster

124.10 - Efficient MCMM Timing ECO on Hierarchical SoC Design with Multiple Variable Voltage Domain

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.11 - End-to-end Verification with Portable Stimulus on Mixed Signal DSP & Automotive SoCs

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.12 - Spice based Big Data Analysis for Optimal Timing Signoff on IoT Design

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.13 - Reset Domain Crossing Design Bugs: The New CDC

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.14 - Six Proven Ideas from the Field for Scalable, Reproducible Design Flows

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.15 - A Modular Approach for Formally Verifying Cache Implementations

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session

Designer and IP Track Poster

124.16 - Mixed-signal Assertion Automation for Circuit Verification

5:00 PM–6:00 PM Jun 26, 2018 (America - Los Angeles)

Designer IP Poster Session