Full custom layout remains an art which is the final milestone of a good IP design. The increasing complexity of new technologies like FDSOI / FINFET, lower technology nodes and increased design features poses multiple challenges. We have developed flows using Cadence tools and our automation that helps to manages above challenges and still work productively. In this paper we describe various features used along with automation techniques for productivity gain in both placement and routing. Some key features developed with strong EDA collaboration like IO ring placement, Schematic Placement of Devices (SPD) and Pin2Trunk routing (P2T) are explained.