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Description
The race to gain silicon market share in the Enterprise space prompts semiconductor companies to develop SoCs with communication interfaces that provide scalability, reliability and high performance while enjoying broad market adoption. Since the early 2000, PCI Express has established itself as the de-facto standard for high-speed chip-to-chip interconnect. In this presentation we look at the upcoming PCIe 5.0 specification and its positioning in the boiling market of high speed interfaces. We review the challenges and pitfalls associated with the implementation of the PCIe 5.0 interface protocol and provide some guidelines for successful integration in tomorrow’s SoCs.
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