Jitter is described as the short term variation of a signal with respect to the ideal position in time, it mainly occurs due to Inter Symbol Interference, Noise. Clock and Data Recovery based circuit’s needs to be verified to ensure that they meet the jitter tolerance and can track the frequency offset limits. Verifying the timing jitter impact is very critical to ensure reliable working of circuits in all conditions. We propose a scalable UVM approach to verify jitter impact and tolerance by using a generic, parameterized Jitter Models on any serial interface which deploy Clock-Data-Recovery based Rx Data-Path.