The high performance integrated circuit have very often high speed interface (SDRAM, QSPI,…). The parasitic elements of the package and the bonding wires can affect the performance of the whole chip if they are not taken into account during the design process.Power-Integrity and Signal-Integrity analyses are closely linked and can NOT be considered separately. These analyses are performed at the full-chip level.The huge amount of data to handle needs to use tools able to take into account die, interconnections... This presentation shows how to use such tool like ANSYS-CSM to check the power integrity of an 32-bit ARM microcontroller