Emerging technologies and new design techniques pose new challenges for test methods but also provide new opportunities. Additionally, current test technologies continue to be stressed by the growing complexity of silicon systems. The first two papers in this session cover advances in soft-error mitigation through a latch design resilient to both single even double upsets and single event transients, and through validation using an efficient method for hardware-based fault injections. The continued increase of test data volume requires new solutions for test compression which is the topic of the third paper. In the final paper, the inherent parallelisms and tolerance to inaccuracies of hardware accelerators can be exploited to offer new alternatives for recovery from defects.