DAC 2018 - Tagged with Keywords>Physical Design & DFM

Research Reviewed

12.1 - WB-Trees: A Topological Representation for FinFET-Based Analog Layout Designs

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 3018

Research Reviewed

12.2 - Analog Placement with Current Flow and Symmetry Constraints using PCP-SP

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 3018

Research Reviewed

12.3 - Multi-Objective Bayesian Optimization for Analog/RF Circuit Synthesis

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 3018

Research Reviewed

12.4 - Calibrating Process Variation at System Level with In-Situ Low-Precision Transfer Learning for Analog Neural Network Processors

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 3018

Designer Track Reviewed

17.1 - Fast Timing Data Analysis for Better Performance, Power and Area on High Performance Computing Design

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 2010

Designer Track Reviewed

17.2 - A Divergence Engine: Early Prediction of Clock-tree Divergence at Logic-synthesis Stage

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 2010

Designer Track Reviewed

17.3 - Load-aware Assertion Generation for Sub-blocks in Hierarchical Timing Optimization and Sign-off

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 2010

Designer Track Reviewed

17.4 - Clock-level Scheduling Technique for Lowering Dynamic Voltage Drop Hot-spot

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 2010

Designer Track Reviewed

17.5 - Asymmetric Aging Timing Check in SOC

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 2010

Designer Track Reviewed

17.6 - Dynamic ESD Analysis for Design Optimization and ESD Sign-off

10:30 AM–12:00 PM Jun 26, 2018 (America - Los Angeles)

Room 2010

Special Session

24.1 - Reducing Time and Effort in IC Implementation: A Roadmap of Challenges and Solutions

1:30 PM–3:00 PM Jun 26, 2018 (America - Los Angeles)

Room 3024

Special Session

24.2 - Efficient Reinforcement Learning for Automating Human Decision-Making in SoC Design

1:30 PM–3:00 PM Jun 26, 2018 (America - Los Angeles)

Room 3024

Special Session

24.3 - Machine-learning Opportunities in Design Automation

1:30 PM–3:00 PM Jun 26, 2018 (America - Los Angeles)

Room 3024

Designer Track Invited

25.1 - Design Challenges and Comparison of Advanced Process Nodes and A Deep Dive Into Custom Hardware Development

1:30 PM–3:00 PM Jun 26, 2018 (America - Los Angeles)

Room 2012

Designer Track Invited

25.2 - Designing Amazing Products on the Worlds Most Advanced Technology Platforms, What it Takes to win at 7nm and Beyond

1:30 PM–3:00 PM Jun 26, 2018 (America - Los Angeles)

Room 2012

Designer Track Invited

25.3 - Memory and Custom Digital Design Challenges in 10nm and 7nm Technology Nodes

1:30 PM–3:00 PM Jun 26, 2018 (America - Los Angeles)

Room 2012

Research Reviewed

29.1 - Exact Algorithms for Delay-Bounded Steiner Arborescences

3:30 PM–5:30 PM Jun 26, 2018 (America - Los Angeles)

Room 3018

Research Reviewed

29.2 - Efficient Multi-Layer Obstacle-Avoiding Region-to-Region Rectilinear Steiner Tree Construction

3:30 PM–5:30 PM Jun 26, 2018 (America - Los Angeles)

Room 3018

Research Reviewed

29.3 - Obstacle-Avoiding Open-Net Connector with Precise Shortest Distance Estimation

3:30 PM–5:30 PM Jun 26, 2018 (America - Los Angeles)

Room 3018

Research Reviewed

29.4 - COSAT: Congestion, Obstacle, and Slew Aware Tree Construction for Multiple Power Domain Design

3:30 PM–5:30 PM Jun 26, 2018 (America - Los Angeles)

Room 3018