DAC 2018 - Tagged with Keywords>Logic & High-Level Synthesis

Research Reviewed

21.1 - A General Graph Based Pessimism Reduction Framework for Design Optimization of Timing Closure

1:30 PM–3:00 PM Jun 26, 2018

Research Reviewed

21.2 - VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units

1:30 PM–3:00 PM Jun 26, 2018

Research Reviewed

21.3 - Noise-Aware DVFS Transition Sequence Optimization for Battery-Powered IoT Devices

1:30 PM–3:00 PM Jun 26, 2018

Research Reviewed

21.4 - Accurate Processor-Level Wirelength Distribution Model for Technology Pathfinding Using a Modernized Interpretation of Rent’s Rule

1:30 PM–3:00 PM Jun 26, 2018

Special Session

24.1 - Reducing Time and Effort in IC Implementation: A Roadmap of Challenges and Solutions

1:30 PM–3:00 PM Jun 26, 2018

Special Session

24.2 - Efficient Reinforcement Learning for Automating Human Decision-Making in SoC Design

1:30 PM–3:00 PM Jun 26, 2018

Special Session

24.3 - Machine-learning Opportunities in Design Automation

1:30 PM–3:00 PM Jun 26, 2018

Research Reviewed

31.1 - Developing Synthesis Flows Without Human Knowledge

3:30 PM–5:30 PM Jun 26, 2018

Research Reviewed

31.2 - Efficient Computation of ECO Patch Functions

3:30 PM–5:30 PM Jun 26, 2018

Research Reviewed

31.3 - Canonical Computation Without Canonical Representation

3:30 PM–5:30 PM Jun 26, 2018

Research Reviewed

31.4 - SAT Based Exact Synthesis Using DAG Topology Families

3:30 PM–5:30 PM Jun 26, 2018

Research Reviewed

31.5 - Efficient Batch Statistical Error Estimation for Iterative Multi-Level Approximate Logic Synthesis

3:30 PM–5:30 PM Jun 26, 2018

Research Reviewed

31.6 - BLASYS: Approximate Logic Synthesis Using Boolean Matrix Factorization

3:30 PM–5:30 PM Jun 26, 2018

Designer Track Reviewed

42.1 - Timing Modeling Methodology for Formal Verification Tools

10:30 AM–12:00 PM Jun 27, 2018

Designer Track Reviewed

42.2 - Acceleration Method of Sequential Equivalence Check in High-Level Synthesis Design Flow

10:30 AM–12:00 PM Jun 27, 2018

Designer Track Reviewed

42.3 - Formally Checking Legality of Firmware Instructions and their Combinations

10:30 AM–12:00 PM Jun 27, 2018

Designer Track Reviewed

42.4 - Fight Fire with Formal Verification

10:30 AM–12:00 PM Jun 27, 2018

Designer Track Reviewed

42.5 - Formal Signoff Meets Real-world Tapeout Schedules

10:30 AM–12:00 PM Jun 27, 2018

Designer Track Reviewed

42.6 - Convergence Techniques for C vs. RTL Equivalence Checking

10:30 AM–12:00 PM Jun 27, 2018

Designer Track Reviewed

51.1 - Replay Mode for Coverage Closure and Efficient Debug

1:30 PM–3:00 PM Jun 27, 2018