DAC 2018 - Tagged with Event Type>IP Track Reviewed

IP Track Reviewed

35.1 - Learning to Share - Embedded FPGA Timing Closure

3:30 PM–5:00 PM Jun 26, 2018

IP Track Reviewed

35.2 - Accurate System-level RNM modelling in Multi-gigabit-transceivers

3:30 PM–5:00 PM Jun 26, 2018

IP Track Reviewed

35.3 - FPGA Bitstream-to-RTL Verification: A Case Study On An IP Module For Aerospace Applications

3:30 PM–5:00 PM Jun 26, 2018

IP Track Reviewed

35.4 - Myths of System Resilience

3:30 PM–5:00 PM Jun 26, 2018

IP Track Reviewed

35.5 - Machine Vision IP Reference System with Intel Architecture (IA) + FPGA

3:30 PM–5:00 PM Jun 26, 2018

IP Track Reviewed

35.6 - ACAI: Arm Coherent Accelerator Interface

3:30 PM–5:00 PM Jun 26, 2018

IP Track Reviewed

62.1 - Topology Specification Management based on IP-XACT

3:30 PM–5:00 PM Jun 27, 2018

IP Track Reviewed

62.2 - Overcoming RTL: The Most-adaptable Open-source RISC-V Core

3:30 PM–5:00 PM Jun 27, 2018

IP Track Reviewed

62.3 - Putting the I in PLM: IPLM Enables a Connected Requirements-driven SoC Methodology

3:30 PM–5:00 PM Jun 27, 2018

IP Track Reviewed

62.4 - An Automated Approach for FPU Arithmetic C-RTL Formal Verification

3:30 PM–5:00 PM Jun 27, 2018

IP Track Reviewed

62.5 - Machine Learning in Arm CPU Verification

3:30 PM–5:00 PM Jun 27, 2018

IP Track Reviewed

62.6 - Towards Fault Resilient System IP Design

3:30 PM–5:00 PM Jun 27, 2018

IP Track Reviewed

Session 35: New Challenges for IP and VIP to Support Emerging Application or Algorithm

3:30 PM–5:00 PM Jun 26, 2018

IP Track Reviewed

Session 62: Innovative Solutions for Typical IP Challenges

3:30 PM–5:00 PM Jun 27, 2018