DAC 2018 - Tagged with Event Type>Designer Track Reviewed

Designer Track Reviewed

1.1 - System Performance and Optimizations for Deep Learning

10:30 AM–12:00 PM Jun 25, 2018

Designer Track Reviewed

1.2 - INSPEX: Integrated Portable Multi-sensor Obstacle Detection Device. Application to Navigation for Visually Impaired People

10:30 AM–12:00 PM Jun 25, 2018

Designer Track Reviewed

1.3 - Energy-efficient Voice Recognition on Constrained Devices

10:30 AM–12:00 PM Jun 25, 2018

Designer Track Reviewed

1.4 - Layered Security: Flexible Application of Embedded RoT & Camouflaged Designs

10:30 AM–12:00 PM Jun 25, 2018

Designer Track Reviewed

1.5 - Extended CPS Simulation for EMC Compliance of Automotive IC Chip Developments

10:30 AM–12:00 PM Jun 25, 2018

Designer Track Reviewed

1.6 - Machine Learning Inference on Arm Client and Embedded Devices

10:30 AM–12:00 PM Jun 25, 2018

Designer Track Reviewed

17.1 - Fast Timing Data Analysis for Better Performance, Power and Area on High Performance Computing Design

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Reviewed

17.2 - A Divergence Engine: Early Prediction of Clock-tree Divergence at Logic-synthesis Stage

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Reviewed

17.3 - Load-aware Assertion Generation for Sub-blocks in Hierarchical Timing Optimization and Sign-off

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Reviewed

17.4 - Clock-level Scheduling Technique for Lowering Dynamic Voltage Drop Hot-spot

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Reviewed

17.5 - Asymmetric Aging Timing Check in SOC

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Reviewed

17.6 - Dynamic ESD Analysis for Design Optimization and ESD Sign-off

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Reviewed

34.1 - Micgelo : A Proven Flow to Reduce Clock Tree Power with Fast TAT

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Reviewed

34.2 - Efficient Power Aware DFT Methodology to Handle Implementation Challenges

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Reviewed

34.3 - Differential Energy Analysis For Improved Performance/Watt In Mobile GPU

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Reviewed

34.4 - A Bottom-up Methodology to Evaluate Silicon Power Consumption for a Large Number of Application-specific Scenarios

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Reviewed

34.4 - A Low-latency and Platform Independent Neuronal Network Design

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Reviewed

34.5 - A Special-purpose Instruction Set and Microarchitecture for Low-power, Dynamic IoT Communication

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Reviewed

34.6 - The Quest for Easy Power-aware SW Development: A Novel Approach to DSP Code Profiling for Energy/Performance Tradeoffs

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Reviewed

4.1 - Ultra Low Power True Single Phase Master Slave Flip-Flop Architectures - A Case for its Usage in Energy-efficient Designs

1:30 PM–3:00 PM Jun 25, 2018