DAC 2018 - Tagged with Event Type>Designer Track Invited

Designer Track Invited

16.1 - A Buggy SoC Framework for Security Assurance Research –Hack@DAC 2018 Case Study

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Invited

16.2 - Finalist team 1 from 2018 Hack@DAC presents their approach - Hackin' Aggies

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Invited

16.3 - Finalist team 2 from 2018 Hack@DAC presents their approach - TRELA

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Invited

16.4 - Finalist team 3 from 2018 Hack@DAC presents their approach - TPTSIC

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Invited

16.5 - Finalist team 4 from 2018 Hack@DAC presents their approach - Dallas Bugboys

10:30 AM–12:00 PM Jun 26, 2018

Designer Track Invited

25.1 - Design Challenges and Comparison of Advanced Process Nodes and A Deep Dive Into Custom Hardware Development

1:30 PM–3:00 PM Jun 26, 2018

Designer Track Invited

25.2 - Designing Amazing Products on the Worlds Most Advanced Technology Platforms, What it Takes to win at 7nm and Beyond

1:30 PM–3:00 PM Jun 26, 2018

Designer Track Invited

25.3 - Memory and Custom Digital Design Challenges in 10nm and 7nm Technology Nodes

1:30 PM–3:00 PM Jun 26, 2018

Designer Track Invited

33.1 - Hardware Security for High Consequence Systems

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Invited

33.2 - Securing Hardware Design: Challenges and Opportunities

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Invited

33.3 - Designing Security into Commercial Products

3:30 PM–5:00 PM Jun 26, 2018

Designer Track Invited

43.1 - Machine Learning Takes Speech Recognition Performance to the Next Level

10:30 AM–12:00 PM Jun 27, 2018

Designer Track Invited

43.2 - Machine Learning for Embedded Image Processing

10:30 AM–12:00 PM Jun 27, 2018

Designer Track Invited

43.3 - Machine Learning on Application Processors (MPU’s)

10:30 AM–12:00 PM Jun 27, 2018

Designer Track Invited

5.1 - The Loihi Research Chip: A Step Towards Scalable and Efficient On-Chip Learning

1:30 PM–3:00 PM Jun 25, 2018

Designer Track Invited

52.1 - Implementation Challenges for Modern Low Power Chip Design

1:30 PM–3:00 PM Jun 27, 2018

Designer Track Invited

52.2 - Low Power Flow/Methodology

1:30 PM–3:00 PM Jun 27, 2018

Designer Track Invited

52.3 - Low Power Sign-off Verification Challenges

1:30 PM–3:00 PM Jun 27, 2018

Designer Track Invited

5.2 - Systematic Solution for Edge Deep Learning: From Accelerator to Software Eco-System

1:30 PM–3:00 PM Jun 25, 2018

Designer Track Invited

5.3 - Benchmark Data Driven Co-design for Neural Network Applications

1:30 PM–3:00 PM Jun 25, 2018