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2018 DAC Art Show
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Maxime Montoya
Agenda
120.7 - Lightweight and Secure Scheme to Mitigate Denial-Of-Sleep on Wake-Up Radios for IoT Devices
Bert Moons
Agenda
45.1 - TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs
Jason Moore
Steve Moore
Agenda
21.4 - Accurate Processor-Level Wirelength Distribution Model for Technology Pathfinding Using a Modernized Interpretation of Rent’s Rule
Dominique Morche
Agenda
121.41 - Methodology Support and Evaluation for Precise Timing Spiking Computation Architectures
Tali Moreshet
Agenda
121.22 - IgnoreTM: Ignoring Timing Violations With Transactional Memory
Daniel Morris
Agenda
81.9 - Towards a Beyond CMOS Logic at 100 mV: Magneto-electric Spin Orbit Logic
Matthew Morrison
Agenda
81.11 - Behavioral Verification and Crossing Reduction Algorithms for pNML Devices
Andreas Moshovos
Professor
at
University of Toronto
Agenda
19.4 - Loom: Exploiting Weight and Activation Precisions to Accelerate Convolutional Neural Networks
81.8 - Bit-Tactical: Exploiting Ineffectual Computations in Convolutional Neural Networks: Which, Why, and How
Mischa Möstl
TU Braunschweig
Agenda
55.3 - Cross-Layer Dependency Analysis with Timing Dependence Graphs
Akshay Mote
Agenda
123.25 - Multi-cycle Path Exceptions Automation and Verification Methodology
Ahmed Mousa
Agenda
71.2 - TMA: An Efficient Timestamp-Based Monitoring Approach to Test Timing Constraints of Cyber-Physical Systems
Artur Mrowca
PhD Student
at
BMW Group
Agenda
55.6 - Automated Interpretation and Reduction of In-Vehicle Network Traces at a Large Scale
Burhan Ahmad Mudassar
Agenda
71.4 - Edge-Cloud Collaborative Processing for Intelligent Internet of Things: A Case Study on Smart Surveillance
Uday Shankar Mudigonda
Agenda
125.7 - FLEX HTREE: Solution for Obstacle Aware Symmetrical Top Level of Clock Trees
Haritha Mudimela
Agenda
7.6 - Graph Databases to Enable High Performance Microprocessor Design
Ranganadh Mudumbai
Agenda
125.7 - FLEX HTREE: Solution for Obstacle Aware Symmetrical Top Level of Clock Trees
Markus Mueller
Agenda
35.2 - Accurate System-level RNM modelling in Multi-gigabit-transceivers
Hannes Muhr
Agenda
34.4 - A Low-latency and Platform Independent Neuronal Network Design
Aditya Mukherjee
Microsoft Corporation
Agenda
Session 6: Minimizing IC Power Consumption with PPA Optimized IPs
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