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Last Name First Name Company State Country Updated

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Maxime Montoya

  • Agenda
    • 120.7 - Lightweight and Secure Scheme to Mitigate Denial-Of-Sleep on Wake-Up Radios for IoT Devices
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Bert Moons

  • Agenda
    • 45.1 - TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs
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Jason Moore

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Steve Moore

  • Agenda
    • 21.4 - Accurate Processor-Level Wirelength Distribution Model for Technology Pathfinding Using a Modernized Interpretation of Rent’s Rule
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Dominique Morche

  • Agenda
    • 121.41 - Methodology Support and Evaluation for Precise Timing Spiking Computation Architectures
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Tali Moreshet

  • Agenda
    • 121.22 - IgnoreTM: Ignoring Timing Violations With Transactional Memory
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Daniel Morris

  • Agenda
    • 81.9 - Towards a Beyond CMOS Logic at 100 mV: Magneto-electric Spin Orbit Logic
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Matthew Morrison

  • Agenda
    • 81.11 - Behavioral Verification and Crossing Reduction Algorithms for pNML Devices
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Andreas Moshovos

Professor at University of Toronto

  • Agenda
    • 19.4 - Loom: Exploiting Weight and Activation Precisions to Accelerate Convolutional Neural Networks
    • 81.8 - Bit-Tactical: Exploiting Ineffectual Computations in Convolutional Neural Networks: Which, Why, and How
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Mischa Möstl

TU Braunschweig

  • Agenda
    • 55.3 - Cross-Layer Dependency Analysis with Timing Dependence Graphs
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Akshay Mote

  • Agenda
    • 123.25 - Multi-cycle Path Exceptions Automation and Verification Methodology
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Ahmed Mousa

  • Agenda
    • 71.2 - TMA: An Efficient Timestamp-Based Monitoring Approach to Test Timing Constraints of Cyber-Physical Systems
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Artur Mrowca

PhD Student at BMW Group

  • Agenda
    • 55.6 - Automated Interpretation and Reduction of In-Vehicle Network Traces at a Large Scale
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Burhan Ahmad Mudassar

  • Agenda
    • 71.4 - Edge-Cloud Collaborative Processing for Intelligent Internet of Things: A Case Study on Smart Surveillance
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Uday Shankar Mudigonda

  • Agenda
    • 125.7 - FLEX HTREE: Solution for Obstacle Aware Symmetrical Top Level of Clock Trees
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Haritha Mudimela

  • Agenda
    • 7.6 - Graph Databases to Enable High Performance Microprocessor Design
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Ranganadh Mudumbai

  • Agenda
    • 125.7 - FLEX HTREE: Solution for Obstacle Aware Symmetrical Top Level of Clock Trees
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Markus Mueller

  • Agenda
    • 35.2 - Accurate System-level RNM modelling in Multi-gigabit-transceivers
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Hannes Muhr

  • Agenda
    • 34.4 - A Low-latency and Platform Independent Neuronal Network Design
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Aditya Mukherjee

Microsoft Corporation

  • Agenda
    • Session 6: Minimizing IC Power Consumption with PPA Optimized IPs
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