DAC 2018 - Speakers/Authors

Arnab Bag

Mukesh Bagul

SMTS at GLOBALFOUNDRIES

Agenda
- 125.26 - Hybrid Clock Tree Planner

Iris Bahar

Agenda
- Session 31: 6 Shades of Synthesis
- 121.22 - IgnoreTM: Ignoring Timing Violations With Transactional Memory

Kangjun Bai

Yu Bai

Brian Bailey

Semiconductor Engineering

Agenda
- Session 26: Have Verification and Validation Engines Become a Commodity?

Janam Bakshi

Design Enablement Engineer at GLOBALFOUNDRIES

Vishnu Balan

Agenda
- Session 78: Is It About Time to Take Inductance and Electromagnetic Effects on SoC Seriously?

Prasanna Balaprakash

Argonne National Laboratory

Agenda
- 81.2 - Machine Learning Guided Application Error Analysis for Efficient Cross-Layer Resilience

Felice Balarin

Mr Lakshmanan Balasubramanian

AMS Lead, & Member, Group Technical Staff at Texas Instruments India Pvt. Ltd.

Agenda
- 51.3 - Novel Pulse Width Insensitive Design and Verification Methods

Mahesh Balasubramanian

Agenda
- 67.1 - RAMP: Resource-Aware Mapping for CGRAs

Matthew Ballance

Technical Marketing Engineer at Mentor,A Siemens Business

Agenda
- 124.29 - Reusing Test Firmware from IP to SoC

Lennart Bamberg

Agenda
- 20.3 - Coding Approach for Low-Power 3D Interconnects
- 120.41 - Exploiting Temporal Misalignment to Increase the Interconnect Performance for 3D Integration

Vitor Bandeira

Agenda
- 79.5 - Extensive Evaluation of Programming Models and ISAs Impact on Multicore Soft Error Reliability

Heerak Bandopadhyay

Agenda
- 124.3 - Novel Method for Prognosis of Plausible IR Violation Prone Regions in SOC

Inyoung Bang

Daniel Bankman

Agenda
- 45.1 - TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs

Shashidhara Bapat

Agenda
- 123.12 - Power Integrity of Large 3D ICs

Naveen Bapu