DAC 2018 - Speakers/Authors

Elad Alon

Agenda
- 41.2 - Enabling Generator-Based Design

Rakshith Amarnath

Agenda
- 22.1 - Semi-automatic Safety Analysis and Optimization

Luca Amarù

Alon Amid

Agenda
- 72.3 - Co-Design of Deep Neural Nets and Neural Net Accelerators for Embedded Vision Applications

Mohammad Amir

Agenda
- 121.32 - Edge-Host Partitioning of Deep Neural Networks With Feature Space Encoding for Resource-Constrained Internet-of-Things Platforms

Hussam Amrouch

Agenda
- 37.4 - Aging-Constrained Performance Optimization for Multi Cores

Dhananjay Anand

Agenda
- 71.2 - TMA: An Efficient Timestamp-Based Monitoring Approach to Test Timing Constraints of Cyber-Physical Systems

Puneet Anand

Staff Engineer at Qualcomm

San Diego California UNITED STATES

Agenda
- 42.5 - Formal Signoff Meets Real-world Tapeout Schedules

Ashok Anbalan

Jason Anderson

Hugo Andrade

Agenda
- 71.2 - TMA: An Efficient Timestamp-Based Monitoring Approach to Test Timing Constraints of Cyber-Physical Systems

Jason Andrews

Solutions Director at ARM

Agenda
- 1.6 - Machine Learning Inference on Arm Client and Embedded Devices

Ravindra Aneja

Sr. Application Engineering Manager at Synopsys,Inc.

Mountain View CA UNITED STATES

Agenda
- Session 51: New Directions in Simulation and Formal

Shaahin Angizi

Agenda
- 56.3 - CMP-PIM: An Energy-Efficient Comparator-Based Processing-In-Memory Neural Network Accelerator
- 76.1 - PIMA-Logic: A Novel Processing-in-Memory Architecture for Highly Flexible and Energy-Efficient Logic Computation

Yilmaz Ar

Agenda
- 81.3 - Mapping Application-Specific Topology to Reconfigurable Mesh Topology

Ismail Emre Araci

Agenda
- 76.2 - Columba S: A Scalable Co-Layout Design Automation Tool for Microfluidic Large-Scale Integration

Somshekhar Arakeri

Agenda
- 125.8 - Improving Design Performance Comprehending Dynamic Voltage Drop Effect

Laurent Arditi

Agenda
- 42.4 - Fight Fire with Formal Verification

Mohammed Arif

Agenda
- 124.9 - A Comprehensive Approach to Clock and Reset Domain Crossing Analysis Sign-off

Vincent Arnoux

Agenda
- 7.1 - Fast Foundry-certified In-design and Signoff Lithography Physical Analysis based on OPC Production Model, Recipe and Engine