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Position
Sr. Verification Engineer
Company
elitePLUS Semiconductor Technologies
Bio

ASIC Verification Engineer
3.5+ Years of experience in, • Block & System level verification using re-usable verification components. • Development & Execution of Test Plan, Code Coverage, Functional coverage. Specialties: Operating Systems: Linux, Windows Programming Languages: C++ HDL Language: VHDL,Verilog. HVL: SystemVerilog HVL Methodology : UVM Protocol Knowledge : AMBA-AHB ,AMBA-AHB Lite,USB2.0,USB3.0,HSIC,AXI,I2C,SMBus,PMBus. Version Control Tool: CVS,Perfoce,Git Hub. Documentation Tool: Doxygen Scripting: cShell,Perl. EDA Tools : IUS,VCS,Questa Sim

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