Engineering Manager

Engineering Manager
ASIC design professional with around 15 years(5 yrs in US-San Jose/Dallas and 1 yr in Europe) of rich experience in ASIC designing, Power management, RTL Integration, Design Flows & methodologies, EDA flow development and deployment, delivery management and in developing innovative technology-based solutions with best in class product quality and easy adopt ability. Known for collaborative problem-solving and meeting challenging project objectives on time and with best quality. Technical expertise in Front-End designing including UPF2.0 enablement for VCLP, VCS, Zebu, SoC-CDC, Low-power Equivalence, synthesis, RTL designing (bus interface protocols), formal verification, logical equivalence, pre-mask Conformal-ECO, power management using UPF/CPF/1801 standards, power verification, power estimation, RTL lint checking, Logical and Physical Synthesis, Pre-CTS, Anallog Design/Layout, Clock-domain crossing, Timing Exception validation, SDC validation, SOC Intergation.

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