0
Position
AMS Lead, & Member, Group Technical Staff
Company
Texas Instruments India Pvt. Ltd.
Bio

Member, Group Technical Staff at Texas Instruments, Senior Member IEEE, MIET, CEng (EngC UK), IPRA & PRI at The IET
~17 years of professional and research experience and accomplishments in the primary and allied areas of analog and mixed-signal SoC & semiconductor IC design, verification, test and related methodologies with passion towards quality and efficiency improvement. End products include single chip hearing aid, multi-radio connectivity ICs with embedded power management, and ultra low power / lost cost mixed-signal microcontrollers. I. Circuit design (>10 products): * Transistor level design of circuits and systems: Custom digital & analog power management circuits * Custom layout and physical design II. Simulation based verification of AMS Circuits and systems (20+ products) * SPICE, Spectre and fast spice based AMS co-simulation * Assertions based verification of analog circuits * Analog behavioural modelling * Formal methods for validation and verification of AMS circuits III. DFX of mixed signal SoC (>5 products) * Analog DFT, design for IDDQ * Design for Qualification / Reliability * Accelerated stress test techniques: HTOL & BI * Analog fault simulation applied to fault grading, test optimisation and diagnosis * Signal integrity: Especially IR drop & substrate noise analysis and reduction * Package stress effects IV. Silicon validation and characterisation of analog contents in mixed signal SoC (>5 products) * Analog test optimisation V. Methodology champion for analog IP design, verification, delivery, SoC integration and test process strategies * Efficiency improvement champion: Process, simulation and iteration effort control * Quality champion: Checklists, automated checkers and sign-off * Silicon failure debug, root-cause analysis and irreversible corrective actions/measures (>15 products) * Static circuit topology checks, Analog verification coverage, Power management & power domain integrity, Stress test optimisation / customisation, Novel fast / early simulation techniques * Analog fault simulation and its applications * AMS BIST and test optimisation

Interests
None yet.