Company Overview
Blue Pearl’s Visual Verification Suite provides FPGA, ASIC and IP developers with HDL design creation as well as advanced integrated RTL linting, constraint generation and clock and reset domain crossing analysis and debug environment, so that designers can verify as they code. With the suite, RTL developers produce the highest level of quality code, in the least amount of time. It is proven to help avoid costly and time consuming design re-spins due to simulation vs. hardware mismatches, structural issues, invalid constraints and metastability issues.

Product Description: FPGA/PLD,Formal Analysis,RTL Design and Entry,Verification,Design Services

Contact (1)
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Jennifer Treiber

Director of Operations at Blue Pearl Software