Entasys has been an EDA solutions provider of the RTL design planning solutions and the design inspection solutions.
Entasys introduces a new and innovative critical path analysis tool for the transistor level design: TRASTA. TRASTA will help designers to identify the critical path automatically. TRASTA extracts SPICE netlist for the critical path and it enables the designers to simulate the circuit within a short time while the whole circuit is very difficult to simulate within a given time, if not impossible.
Entasys also presents the new version of early design planning solution: NavisPro. NavisPro is the power and timing aware hierarchical RTL design planning solution which predicts and prevents the physical implementation problems in early design stage. The hierarchical RTL floorplanning feature is newly added functionality to the existing solution and it enables the designers to effectively plan the top level design considering the sub chip design. In addition, NavisPro supports the design constrains management including clock structure exploration, power constraints validation and power state aware power estimation.
Product Description: RTL Design and Entry,Silicon Virtual Prototype