Agnisys Inc. is leading supplier of Electronic Design Automation (EDA) software for solving complex design and verification problems for system development. Its products provide a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) enabling faster design, verification, firmware, and validation. Based on patented technology and intuitive user interfaces, its products increase productivity and efficiency while eliminating system design and verification errors.
Founded in 2007, Agnisys is based in Boston, Massachusetts, with R&D centers in the United States and India.
For more details visit: www.agnisys.com
About our tools
Innovative, High-Performance ASIC, FPGA and SoC software to solve complex design and verification problems
IDesignSpec™ (IDS): Create Executable Design Code from the Specification
IDesignSpec is an award-winning software that helps IP/SoC design architects and engineers create simple, yet powerful specifications described in the plain text, MS Word, Excel or Libre Office. It captures simple as well as special registers, signals, interrupts and sequences, then generates synthesizable client interfaces for ARM AMBA® buses like AXI, AHB, APB, AHB3Lite etc. IDS also generate UVM models & provide firmware code and enables software teams to develop the device driver at the early stage of the design cycle.
ISequenceSpec™ (ISS): Portable Sequence Generator for Verification, Firmware & Validation
ISequenceSpec enables users to describe programming and test sequences of a device and automatically generate sequences ready to use from an early design and verification stage to post-silicon validation. A sequence is an algorithm or the “set of steps” that involve writing/reading specific bit fields of the registers in the IP/SoC. These sequences can be simple, or complex involving conditional expressions, an array of registers, loops and more. ISequenceSpec helps the user write a single sequence specification and generate the UVM sequences for verification, Verilog or C sequences for validation and various output formats for Automatic Test Equipment (ATE).
Automatic Register Verification™ (ARV): Simulation & Formal Verification
ARV is a complete register verification solution using complementary methodologies, simulation and formal. ARV-Sim helps to auto-generate UVM testbench, bus agents, monitors, drivers, adaptors, predictors, sequencers, and sequences, giving users the means to complete the verification right the first time. The verification plan allows easy back-annotation from the test results, allowing users to track the progress of verification efforts. ARV-Formal automatically generates assertions directly from the specification.
IDS NextGen™ (IDS-NG): Comprehensive SoC/IP Specification and Code Generation Tool
IDS NextGen is a cross-platform product which helps the user to create SoC specification by an enterprise team. It handles individual IP to sub-system to SoC level and is compatible with Word, Excel, IP-XACT, RALF, CSV, SystemRDL. IDS NextGen cuts the system development time in half by capturing the specification in a simple, easy to use interface, and creating design and verification code with a powerful code generation engine.
DVinsight™: Design Verification Insight
DVinsight is a smart editor for creating correct-by-construction, high-quality design verification testbench code. Code created with DVinsight is UVM standardized and bug-free to avoid time-consuming and costly debugging later in the semiconductor development process. DVinsight helps design verification engineers create correct-by-construction testbench code, it benefits expert developers as well as beginners because it prevents simple mistakes and helps beginners decrease their System Verilog and UVM learning curve.