DAC 2018 - Browse Agenda

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.10 - From how we Tackle NP-Complete to a new ECO Technique Applying Precise "Circuit Surgery"

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.11 - A Fast Library Evaluation Method based on Static Liberty Comparison

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.12 - Power Integrity of Large 3D ICs

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.13 - ISO 26262: How Safe is your Safety Mechanism?

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.14 - Power-efficient Clock Tree Design

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.15 - Hybrid Chip-Level Power Analysis Flow in Mobile Design

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.16 - Early Level Thermal Analysis and Thermal Aware Design Flow

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.17 - Power and Reliability Analysis for Next Generation InFO & CoWoS Style Designs

Level 2 Exhibit Floor

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.18 - A Generic, Fully Automated Physical Verification Methodology for 2.5D-IC

Level 2 Exhibit Floor

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.19 - Increased Productivity Solution for Full Custom Layout

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.1 - Electro-thermal Simulation for Analog Designs

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.20 - Improving Process Uniformity with CMP Aware Fill Insertion Technique

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.21 - Static Timing Analysis Using NanoTime for Custom Circuits

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.22 - Power & Signal Integrity Analysis applied yo 32-bit ARM Microcontroller

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.22 - UVM VIP Framework for Verification of High-Speed Interface Rx Data-Path

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.23 - Embedded FPGA enabling 5G Infrastructure

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.23 - Modeling Clocks, Resets and Power Rails in SoC Functional Simulator

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.24 - Low-resource Cryptography for Highly Constrained IoT Devices

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.25 - Multi-cycle Path Exceptions Automation and Verification Methodology

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.26 - Integrated ESD Solution: How Various ESD Checks can be Integrated in a Single Flow for Efficient Analysis

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.2 - Soft-IPs Protection using Chaotic Map-based Encryption

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.2 - Technical Director, Automotive Applications Engineering

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.3 - High Quality Test with Efficient usage of Optimal Number of I/Os

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.4 - Novel and Configurable Circuit for Post-Silicon Measurement of Dynamic and Leakage Power of Sequential Circuits

Designer IP Poster Session

5:00 PM–6:00 PM

Jun 25, 2018

(America - Los Angeles)

Designer and IP Track Poster

123.5 - Solving the Flash Incompatibility Issue

Designer IP Poster Session

All Sessions