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Description
Designs these days are very large in size and are operating at high frequencies; it has become evident that we need to have very good clocks trees with more common path and almost zero skew to close timing on such chips. In pursue of getting best of both common path and zero skew clocks, earlier we have introduced hybrid clock tree approach methodology. However, this presentation we introduce an hybrid clock tree planner which is automated with editing options which not only eases the implementation of hybrid clock tree with existing methodology but also make it faster.
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