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Description
A case of verifying production DRAM peripheral circuits with automatically-generated SystemVerilog models is presented. SystemVerilog is convenient for verifying top-level digital functionality of DRAMs, but manually writing and maintaining models for ~600 analog/mixed-signal circuit cells can be effort-consuming and error-prone. We developed a flow that automatically generates correct-by-construction structural models by mapping each element in the circuits to an equivalent primitive in Verilog or XMODEL. When applied to the tests of internal voltage generation, power-up initialization, and timing margins, the SystemVerilog simulation achieved 5~7x speed-up compared to using fast SPICE with
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