Late Breaking Results

81.15 - Fault-Tolerant Topology Generation for 3D-NoCs

3:30 PM–5:30 PM Jun 26, 2018 (America - Los Angeles)

Room 3014

In this study, we present a method that generates irregular fault-tolerant topology and reconfigurable routing tables for 3D Network-on-Chips (NoCs). The generated topology allows at least two alternative paths between any communicating pair of application nodes. If there is a permanent link failure on a default path, we can reconfigure the alternative routing table with the smallest increase in latency and energy consumption. We compared the proposed systems with its 2D counterpart on several multimedia benchmarks based on energy consumption and chip area. The results show that 3D-based method brings significant energy and area improvements, especially in alternative routings.