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Description
In order to substantially improve hardware design productivity, reuse should be leveraged dramatically more than traditional design methodologies allow. This paper therefore describes a generator based approach where designers capture their methodologies as executable code, enabling reuse by parameterization and incremental extension of the generators. Our approach supports both digital (via Chisel) as well as analog (via BAG) generators, and was used to design and verify RISC-V processor based mixed-signal SoCs in TSMC’s 16nm FFC technology.
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