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Description

Today’s IC design process faces a crisis of cost and risk. Both human cost (i.e., engineering expertise and effort) and schedule cost (i.e., design schedule) are barriers to leading-edge design. This crisis has spurred new research initiatives that seek to substantially reduce the cost of IC design, even to unprecedented “no-human-in-the-loop” and 24-hour turnaround time levels. This session covers technical aspects of RTL-to-GDSII design effort reduction at the leading edge of EDA and design practice -- today and in the future.

The first talk gives a big picture of how IC design can exploit cloud deployment and machine learning toward “no-human-in-the-loop” design. A talk from Qualcomm then highlights where design effort pain points exist today, as well as experiences with reinforcement learning and flow automation/autotuning. The session concludes with an EDA vendor perspective on opportunities and proof points for how EDA will enable design effort reductions for customers.

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