Modern SoC design has already become an unwieldy compute-intensive beast with multiple bottlenecks threatening tapeout schedules. How must our semiconductor design methodology change to meet the coming wave of billion-instance chips that AI and machine learning will bring? This panel of expert designers, IP providers, and EDA tool vendors will consider the top emerging trends, their design implications, and potential solutions to overcoming these imminent challenges. Topics discussed may include AI/ML trends in HPC, mobile and automotive markets, tool scalability, EDA in the cloud, 20M instance blocks, point tools vs. integrated flows, and physical design to 7nm and below.