Modern SoC’s have multiple functionality in single SoC to perform much complex jobs. Innovative RTL Integration techniques has evolved to reuse and integrate functional blocks efficiently. There is shift to block based design and verification practices. But this approach comes with challenges even if each block is designed properly within its boundaries, each may have been designed using different strategy. Designers have to ensure that top level and inter-block clocking and low power implementations work as expected without leaving signals at block boundaries in unpredictable states. Paper explain challenges in CDC/RDC verification and provide solutions to the most common issue.