In complex SoC implementation, there are lot of signals which passes through several hierarchal partitions to reach it’s intended logic block. Due to long resistive wires there is need to sample this logic at regular intervals with help of pipeline flops. Number of stages are determined with help of SPICE simulations. The setup depend upon routing layer and repeater cell. This process is quite tedious and lengthy. here is risk of over-design. Apogee offers novel approach to auto-insert pipeline flops which takes several user constraints into account and thus reduces time and iterations to determine right number of pipeline flops.