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Description
On-chip ESD verification is a challenging problem and having different ESD testers add to the complexity of the problem. We propose a methodology, implemented in ANSYS PathFinder-D, which accounts for different tester, package models, and on-chip RC coupling effects while keeping SPICE accurate models for the on-chip devices, resulting in higher accuracy of the simulations. This approach provides the flexibility to inject the measured pogo-pin current waveforms and run a transient simulation. The transient simulation generates detailed voltage/current waveforms, junction stress waveforms, current discharge waveforms and stress reports for the designer to review and fix the design prior to tapeout.
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