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Description
Gate-level verification depends heavily on simulation, so any improvements in methodology, infrastructure, and libraries have significant impacts on overall verification throughput and efficiency. This paper presents: • Methodology flow improvements that improve GLS simulation throughput for both single-test modes and regression suites. • Cell modeling guidelines that ensure accurate, error-free modeling and improved GLS throughput efficiency. • A novel test pattern-based partitioning scheme that improves ATPG and BIST test runtimes significantly and enables very fast debug turn-around times. Measured simulation throughput speedups range from 20% to over 4X faster for the flows described in this paper.
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