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Description
SoC designers need accurate power numbers early to close the gap between power budgets and actual consumption derived from realistic design application-specific scenarios. Traditional power sign-off methodologies have various drawbacks: rely on availability of gate-level simulation environments, long runtimes, resource intensive, and available too late in the design cycle. We propose a bottom-up power analysis methodology that addresses these challenges by leveraging simulation-replay technology with an accuracy of a proven signoff tool using readily available RTL simulations. A bottom-up analysis methodology is implemented to realize the goal of running scores of chip configurations and usage models to achieve power targets
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