The presentation will detail our unique interconnect which gives higher density and few metal layers and that enables us to use standard cells (including two that we optimize for eFPGA) for portability while achieving density similar to full-custom FPGA. We’ll also explain how we design an IP core that is a standalone eFPGA but that can be arrayed/tiled with a top level interconnect to make arrays of dozens of sizes up to a 7x7. Finally, we’ll explain how we provide optional DSP and RAM building blocks to be integrated. The end result is an array that uses GDS-proven elements for customer confidence in their chip tape-out. This presentation will also outline the architectural features and eFPGA design tradeoffs involved in the DragonFly System-on-Chip that has been implemented in Sandia’s 180-nm process node, and which uses the EFLX4K eFPGA logic core from Flex Logix Technologies.