Advanced 10nm and 7nm generation CMOS technologies enable substantial increases in transistor density and fundamental improvements in energy efficiency, but there are new challenges in design to unleash the benefits of continued technology scaling. Interconnect emerges as a primary design consideration at these nodes, demanding careful attention in IP planning, power delivery, performance optimization and circuit architecture selection. As most product segments have become power-constrained, from IoT/mobile to datacenter applications, demand for low operating voltage memories is pervasive and requires a careful tradeoff between technology, circuit and architectural techniques to ensure application-appropriate solutions. With continued transistor and interconnect pitch scaling, reliability considerations are becoming a legitimate design consideration in memory and custom digital design domains.