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Designer Track Reviewed

17.3 - Load-aware Assertion Generation for Sub-blocks in Hierarchical Timing Optimization and Sign-off

10:30 AM–12:00 PM Jun 26, 2018

Room 2010

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Author (5)
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Tags
Event TypeDesigner Track Reviewed
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KeywordsPhysical Design & DFM
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Topic AreaDesign
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Topic AreaEDA