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Description
SoC functional simulators are widely used prototyping platforms for early SW-validation before the availability of Silicon. Clocks and power ungating sequences can be tested in very limited way on other prototyping solutions like System FPGA, Emulation. Software teams implementing common drivers for these global functions (clocks, resets, power) need a solution to validate and debug their code well before silicon arrival. We propose a solution to extend traditional SoC function simulator with information on clocks, reset, power rail to enable early System Boot and SW-driver bring-up in a foolproof way.
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