There are a lot of mixed-signal chips being developed due to the explosion of IOT devices. Large portions of mixed signal chips are created by transistors. These are ‘standard cells’ like but at transistor level. NanoTime provides the capability to extract timing for these cells to allow static timing analysis at transistor level. NanoTime supports the extracted spice netlist with transistor model and constraints. By using NanoTime, designer can run complete timing analysis with the same accuracy as spice simulation in different PVT corners. Tool is capable to generate timing models of modules in .lib format.