Modern ASICs contain large of sequential elements - high performance, low power, clock gated etc. Accurate post-silicon power measurement of them in a “SoC-like” implementation is essential, so that these precise power numbers are updated in dotlib, resulting in error-free pre-silicon power estimation of all future SoCs Proposed is a sequential element chain with control on Mode of operation to stay within power measurement range of lab equipment Frequency Data lock activity factor Slew - input Load cap - output Uses separate supply for sequential elements Through intelligent measurement strategies, it helps in achieving perfect model to hardware correlation