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Description
Manufacturing test with minimum I/Os is challenging for present-day designs, which not only require comprehensive testing for achieving very low DPPM without increasing the test cost, but also have fewer functional pins available to share with test. In this paper, we present a low test pin architecture with efficient I/O utilization by re-using the scan I/Os to drive complex sequencing of test signals from the tester instead of internal state machines or other logic which incur significant test logic overhead. With this architecture, we have achieved 25% I/O reduction without any negative impacts to vital testability QoR metrics.
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