SoCs can have thousands of compiled SRAMs with a very wide range of number of bits per memory running at a wide range of frequencies depending on the different IP blocks. The need of the larger SRAM to support repair yield improvement is clear. The point at which the need of multitude of scattered small SRAMs, which can total to a large bit count, for repair is not clear as BIST and repair require die area which can reduce yield per wafer. This presentation will cover the many factors which can affect Yields and product costs for Memories and other complex circuits, data required to make prioritized and weighted trade-off decisions and review architectural features to enable a methodology to support “Smart” trade-off decisions.