Advanced SoC designers are challenged to make the right IP choices for accelerated design cycles while minimizing product risk. Modern SoC’s combine IP’s from a diverse group of disparate sources based on cost, availability, ease of integration and reuse concerns. What about time to ramp and final yield? When first silicon comes out of the fab, multiple engineering resources with skills in test, design, design for test, and functional product must rapidly troubleshoot highly complex problems. Many of the barriers to solving these bring up problems lie in fundamental IP debug—how to communicate and characterize each block of the chip. This presentation summarizes the recent evolution of IJTAG (IEEE 1687) based IP designs and how standardization can improve silicon bring up time and yield ramp.