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In tandem with CMOS technology scaling beyond 28nm and deep into the FinFET era of 7nm and beyond several considerations occurred in CMOS technology and in SOC and IP design that made memory and IP design complicated way beyond the classical redundancy and repair techniques common in memory design to guarantee robust functionality and good yield. FinFET technology practically ended the ability to “fine tune” the beta of an SRAM memory cell. Also, the high K metal gate further altered the BTI balance of Vt shift for P and N devices. Add to that the continued desire to operate at lower VDD levels making SNM narrower and making read and write assist harder to implement. In this talk we will address the implications of these changes taking place on memory design methodology emphasizing redundancy, repair, and reliability strategies.
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