Designer Track Reviewed

Session 7: Finding Patterns and Inferences

3:30 PM–5:00 PM Jun 25, 2018 (America - Los Angeles)

Room 2012

This session explores robust and efficient failure analysis and fix-up techniques to address issues from manufacturability to ESD protection. We start with the use of pattern matching and classification techniques for DFM and memory array verification. We then see how machine learning can be used to aid these computationally intensive steps. This is followed by a fast method to identify CDM failures. We end this session with a view of constructing large-scale graph databases for efficient post-design analyses.
Sub-Sessions ( See all )