This session presents new architecture designs with both DRAM and non-volatile memory technologies. The first two papers describe deep neural network accelerator designs with in-DRAM computing and MLC NVM, respectively. The next two papers describe novel DRAM architectures with variable access-latency and variable refresh-latency. The next paper proposes page cache for performance improvement in NVM-based storage. The final paper presents a technique for QoS-aware scheduling in mobile platforms.
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