DARPA’s new Circuit Realization At Faster Timescales (CRAFT) program has as its goals to reduce by 10X the effort required to design and verify complex SoCs in leading edge CMOS technology and to reduce by 5X the effort required to port designs to a new fabrication process. This session will describe some of the key results from the first 15 month phase of the program, including work performed by teams led by NVidia, UC-Berkeley, and UC-San Diego.