Monday Tutorial

Tutorial 9: Design Tools for Verifying Hardware Security

1:30 PM–5:00 PM Jun 25, 2018 (America - Los Angeles)

Room 3022


Hardware security vulnerabilities are notoriously hard to detect and even more difficult to fix after fabrication. Unfortunately, state-of-the-art secure hardware design process still heavily relies on manual inspection to determine if the design is free of any and every security vulnerability. Hardware designers and verification engineers are in desperate need of tools and techniques to enable deeper and more complete security analysis. In this tutorial, we describe how emerging hardware security verification tools help fill this need. The presentations bridge from theory to practice with the goal of exposing attendees to the latest research while demonstrating the practicality of these techniques to test and verify a variety of different security properties on real hardware designs through security verification.

The 3-hour long tutorial has four expert speakers to present the most recent advances in hardware security verification techniques and tools. There is a focus on how to practically use these tools to secure different parts of the system design including digital hardware and firmware. We start with a session that covers the foundations of hardware security verification (Prof. Tim Sherwood, UC Santa Barbara). Then, we will dive into more details about some of the most prevalent hardware security verification tools; these include SecVerilog/Secure Chisel for processor design (Prof. G. Edward Suh, Cornell), proof carrying hardware for IP protection and analog designs (Prof. Yiorgos Makris, UT Dallas), and utilizing hardware security tools “in the wild” to verify security properties on state of the art hardware designs (Dr. Jason Oberg, Tortuga Logic).