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Research Reviewed

Session 74: Faster, Higher, ...Safer HLS

1:30 PM–3:00 PM Jun 28, 2018 (America - Los Angeles)

Room 3024

Description
The papers in this session innovate high-level synthesis in various directions. The first two papers improve design space exploration through design templates and innovative design frameworks; the third improves design security by making the IPs harder to reverse engineer. The last paper proposes an interesting graph-coloring approach to memory partitioning.
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