In system design we often observe a gap between modern practice and the ideal. In designs dominated by engineering cost, we look for techniques to increase productivity. The first two papers of this session aim at increasing SoC simulation and DSP-design productivity, respectively.
By contrast, the margins required to make our designs robust leave performance on the table. The remaining two papers apply thoughtful scheduling techniques to the problems of reducing the margins on Vdd required for power supply noise and the margins in timing for aging, respectively.