The 1980s enjoyed architectural innovation when high-level language programming surpassed assembly language programming, which made instruction set innovation plausible, and because the Mead-Conway democratized chip design. Innovations like RISC, VLIW, and superscalar doubled performance every 18 months. The following decades saw consolidation, leveraging Moore’s Law via higher clock rates and larger caches. 

The ending of Moore’s Law brought performance to a standstill. Processors improved only 3% last year, taking 20 years to double!  Moreover, the new Spectre security enables timing attacks that leak information at ≥10 kilobits/second. 

The only likely path left is changes in the instruction set architecture (ISA). For example, Domain Specific Accelerators (DSAs) can perform narrow tasks an order of magnitude more efficiently. For proprietary ISAs, we must wait years for improved chips. 

The RISC-V ISA opens another path. The plasticity of FPGAs and free implementations of RISC-V enable experimental investigations of novel architectures deployed and iterated in days. FPGAs are slow but fast enough to run trillions of instructions or be deployed to test against real attacks. 

Unlike proprietary ISAs, everyone can help. For tall challenges like these, we want all the best minds working on them.

We give examples of DSA chips that deliver tenfold improvements in performance-energy and sketch an example of improving RISC-V security by defeating Return Oriented Programming. 

RISC-V’s openness and flexibility can meet the cost-performance-energy-security demands of the Post Moore’s Law era. Freeing architects from the chains of proprietary ISAs may well lead to another Golden Age for computer architecture.